1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device which allows reduction in layout area.
2. Description of the Background Art
A static random access memory (hereinafter referred to as an "SRAM") will be described as an example of a conventional semiconductor device. The SRAM is a volatile semiconductor memory device. In SRAM, memory cell is arranged at each intersection between complementary data lines (bit lines) and word lines arranged in a matrix. FIG. 7 shows an equivalent circuit of a CMOS type memory cell as such memory cell.
Referring to FIG. 7, the memory cell includes a flip-flop circuit F and two access transistors A1 and A2. In flip-flop circuit F, input and output terminals of one inverter consisting of a load element L1 and a driver transistor D1 and of another inverter consisting of a load element L2 and a driver transistor D2 are cross coupled to each other, providing two storage nodes N1 and N2.
Source.cndot.drain region of access transistor A1 is connected to storage node N1. Source.cndot.drain region of access transistor A1 is connected to one of the complementary bit lines. Similarly, source.cndot.drain region of access transistor A2 is connected to storage node N2. Source.cndot.drain region of access transistor A2 is connected to the other one of the complementary bit lines. Driver transistor D1 has its drain region connected to source.cndot.drain region of access transistor A1. Driver transistor D1 has its source region connected to the ground. Driver transistor D1 has its gate electrode connected to source.cndot.drain region of access transistor A2.
Driver transistor D2 has its drain region connected to source.cndot.drain region of access transistor A2. Driver transistor D2 has its source region connected to the ground. Driver transistor D2 has its gate electrode connected to source.cndot.drain region of access transistor A1.
Load element L1 has one end connected to source.cndot.drain region of access transistor A1 and the other end connected to a power supply voltage line (Vcc line). Load element L2 has one end connected to source.cndot.drain region of access transistor A2 and the other end connected to the power supply voltage line (Vcc line). Access transistors A1 and A2 have gate electrodes connected to a word line (WL). The word line (WL) controls conduction of access transistors A1 and A2.
Storage nodes N1 and N2 assume two stable states in which a voltage at one storage node is at the high level and a voltage at the other storage node is at a low level or vice versa. Such a stable state is referred to as bistable state. Because of this bistable state, refreshing operation, which is necessary for a DRAM, is unnecessary in the SRAM, which facilitates use of the SRAM.
In the CMOS type memory cell of the SRAM described above, p channel MOS transistors are used for load element L1 and L2, and n channel MOS transistors are used for driver transistors D1 and D2. Further, n channel MOS transistors are used for access transistors A1 and A2.
Therefore, in one memory cell, six MOS transistors are used. The CMOS type memory cell is advantageous in that it has wide operation margin and extremely low data holding current, and therefore the memory cell is suitable for realizing reduction in voltage.
One memory cell has an NMOS region 104 in which n channel MOS transistors are formed, and a PMOS region 106 in which p channel MOS transistors are formed, as shown in FIG. 8. In NMOS region 104, two driver transistors D1 and D2 as well as two access transistors A1 and A2 are formed, as described above. In PMOS region 106, MOS transistors as two load elements L1 and L2 are formed.
NMOS region 104 and PMOS region 106 are electrically insulated by a field shield isolation, respectively. For this purpose, field shield contact portions 108a and 108b for field shield isolation are formed in NMOS region 104 and PMOS region 106. Further, body contact portions 111a and 110b are formed to fix voltages at portions corresponding to channel regions of the MOS transistors formed in NMOS region 104 and PMOS region 106, respectively.
The structure of the memory cell will be described in greater detail in the following. FIG. 9 schematically shows a planar structure in which one n channel MOS transistor and one p channel MOS transistor are formed, for convenience, in NMOS region 104 and PMOS region 106 of FIG. 8. FIG. shows a cross sectional structure taken along the line A-B-C-D-E-F of FIG. 9.
Referring to FIGS. 9 and 10, NMOS region 104 and PMOS region 106 are formed on a silicon substrate 101 with a silicon oxide film 103 interposed. An n channel MOS transistor including a pair of n type source.cndot.drain regions 116a and 116b as well a transfer gate electrode 114a is formed in NMOS region 104. Below transfer gate electrode 114a, a channel region 117 at which the channel is formed, is positioned.
Surrounding the MOS transistor, a p type region 120 is formed. The p type region 120 is electrically connected to channel region 117.
Further, in order to stabilize an operation of the n channel MOS transistor, a body contact portion 110a for fixing the voltage of channel region 117 to the ground voltage is formed in p type region 120. On p type region 120, a field shield gate electrode layer 122 is formed with a relatively thin silicon oxide film interposed. A field shield contact portion 108a for fixing the field shield gate electrode layer 122 to the ground voltage is formed in field shield gate electrode layer 122.
In PMOS region 106, a p channel MOS transistor including a pair of p type source.cndot.drain regions 118a and 118b as well as a transfer gate electrode 114b is formed. Below transfer gate electrode 114b, a channel region 119 at which the channel is formed, is positioned.
Surrounding the MOS transistor, an n type region 121 is formed. The n type region 121 is electrically connected to channel region 119. Further, a body contact portion 119b for fixing the voltage of channel region 119 at a power supply voltage to stabilize an operation of the p channel MOS transistor is formed in n type region 121. On n type region 121, a field shield gate electrode layer 123 is formed with a relatively thin silicon oxide film interposed. A field shield contact portion 108b for fixing field shield gate electrode layer 123 to the power supply voltage is formed in field shield gate electrode layer 123.
NMOS region 104 and PMOS region 106 are electrically insulated by field shield isolation. On the side of NMOS region 104, by a kind of transistor including p type region 120 and field shield gate electrode 122, field shield gate electrode layer 122 is fixed at the ground voltage, so that the channel region is not formed at p type region 120 below field shield gate electrode layer 122, whereby NMOS region 104 is electrically insulated from other regions.
On the side of PMOS region 106, by a kind of transistor including n type region 121 and field shield gate electrode layer 123, field shield gate electrode layer 123 is fixed at the power supply voltage, so that the channel region is not formed in n type region 121 below field shield gate electrode 123, whereby PMOS region 106 is electrically insulated from other regions. The memory cell of a conventional SRAM has the above described structure.
However, the SRAM described above suffers from the following problems. In the CMOS type SRAM memory cell, six MOS transistors are used per one memory cell. Therefore, though the memory cell is advantageous in that it has wide operation margin and is suitable for reducing voltage, it is disadvantageous that the area occupied by the memory cell is large as compared with other type memory cells such as a high resistance load type memory cell. The high resistance load type memory cell refers to a memory cell which utilizes a high resistance element as a load element in the memory cell.
Further, in the CMOS type SRAM memory cell, two field shield contact portions are formed for every memory cell, in order to electrically insulate NMOS and PMOS regions in the memory cell. Further, in order to stabilize operations of MOS transistors formed in the NMOS and PMOS regions respectively, two body contact portions are formed in every memory cell. Accordingly, in the CMOS type SRAM memory cell, in addition to the region for forming 6 MOS transistors, a region for forming the above described four contact portions is necessary for each memory cell. Therefore, it has been difficult to overcome the disadvantage that the area occupied by the CMOS type memory cell in the SRAM layout is larger than the area occupied by a memory cell of a different type.